SystemVerilog 4-Bit BCD Counter & 7-Segment Decoder: Design Report & Walkthrough ( System Verilog )
A complete design guide for a 4-Bit BCD Counter with 7-Segment Display output. This download includes a technical report and walkthrough covering the SystemVerilog implementation of sequential counting logic (Modulo-10), combinational decoding, and testbench verification with waveform analysis.
The objective of this project is to design and simulate a synchronous digital system using SystemVerilog that functions as a 4-Bit BCD (Binary Coded Decimal) Counter.
The core technical challenge involves implementing specific Modulo-10 logic to restrict the standard 4-bit binary counting range (0–15) to a decade sequence (0–9), ensuring the system correctly resets to zero upon reaching nine. Additionally, the system requires a combinational decoder module to translate the 4-bit binary output into active-high 7-bit control signals suitable for driving a 7-segment display. The final design must be verified through a ModelSim testbench to confirm correct timing, rollover logic, and display mapping.
