A complete SystemVerilog project for a Traffic Light Controller using a Moore Finite State Machine (FSM). This download includes the source code for cycling through Green, Yellow, and Red states , a 7-segment decoder for visual output , and a ModelSim testbench to verify state transitions and timing .
The objective of this project is to design and verify a digital control system for an automated traffic light. Real-world traffic management relies on precise timing and clear visual feedback to maintain safety. The specific technical challenge is to implement a Finite State Machine (FSM) using SystemVerilog that automatically cycles through a fixed sequence of states: Green (G), Yellow (Y), and Red (R).
The system must meet the following requirements:
State Control: The controller must transition states (G → Y → R → G) on every clock cycle when the reset is low ("0") and immediately return to the default Green state when the reset is high ("1").
Visual Output: The design must include a 7-segment decoder that translates the internal 2-bit binary state codes (00, 01, 10) into the corresponding 7-bit binary patterns required to display the characters 'G', 'Y', and 'R' on a common 7-segment display.
Verification: The functionality of both the FSM and the decoder must be verified through waveform analysis in ModelSim to ensure glitch-free transitions and accurate character representation.
